The RMC expects a stop bit after the data is complete. Since the RMc cannot use the status bits, it must send only 10 clock bits. However, it also requires a stop bit to be low after the data. When sending only the 10 bits, the next bit sent by the AMCI is the status bit, not the stop bit.
Another problem is that the AMCI sets the data line low when receiving the first clock pulse. The RMC expects the data line to be high until the first data bit, which is after the second clock pulse.
I called AMCI to verify that the device actually behaves this way. They informed me that it does, and gave me the part number of the chip they use that generates the SSI signal (austriamicrosystems.com/eng/ … ers/AS5043).
We are confused as to why the chipmaker would make an SSI output that is not in line with the SSI standard as originally designed by Stegmann (Synchronous Serial Interface - Wikipedia). Unfortunately, we have been seeing more and more non-standard SSI designs. We hope to eventually make modifications to our SSI design to accommodate some of them, but it is very difficult to foresee what other non-standard changes will be made.
For your constant rotation in one direction, even if it is open loop, it would be much easier to do with a rotary device compatible with the RMC (see SSI Rotary Absolute Encoders). You could perhaps do it with the analog device you have, but then you would have to disable some of the error functionality, and in general it would not be as nice as it otherwise could be.